While semiconductor devices have been used in electronic devices such as computers and cellular phones, semiconductor devices are also increasingly used for high power and high frequency applications such as subscriber cable service transmission and cellular base station transmission. Therefore, one of the goals of the semiconductor industry is to develop semiconductor devices that operate at high frequencies as well as provide adequate power for data transmission applications.
One type of semiconductor device used for high power and high frequency applications is the power metal oxide field effect transistor (MOSFET). Of the various forms of power MOSFETs, the Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS) device is commonly used because of its output power capability and high efficiency. Because of its high performance and efficiency, the LDMOS device has found its way into demanding applications such as cellular phone base stations and other transmission equipment.
As performance requirements have become more demanding, however, semiconductor device manufacturers must continually improve power transistor device performance. One limitation to power transistor device performance is parasitic capacitance. In power transistors, parasitic capacitance is particularly problematic because of the large device structures necessary to source and sink large currents, while avoiding breakdown at high voltages. As device size increases, parasitic capacitance contributors, such as source-substrate capacitance, drain-substrate capacitance, gate-drain capacitance, gate-source capacitance, and interconnect capacitance also increase.
Besides limiting device performance through the mere presence of capacitive loading, practical considerations in dealing with parasitic capacitance may also lead to higher resistive parasitics. For example, in order to maintain a minimum parasitic gate-source capacitance due to the presence of gate routing over the source, the number of gate contacts may have to be reduced. Such a reduction in the number of gate contacts results in a correspondingly higher series gate resistance.
In the field of highly efficient power transistors, device structures that minimize parasitic capacitance are needed.